The mobile computing (e.g., smart phone and tablet) markets benefit from smaller component form factors and lower power consumption. Because contemporary platform solutions for smart phones and tablets rely on multiple packaged integrated circuits (ICs) mounted onto a circuit board, further scaling to smaller and more power efficient form factors is limited. For example, a smart phone will include a separate power management IC (PMIC), radio frequency IC (RFIC), and WiFi/Bluetooth/GPS IC, in addition to a separate logic processor IC. System on Chip (SoC) architectures offer the advantage of scaling, which cannot be matched by board-level component integration. While the logic processor IC may itself be considered a system on a chip (SoC) integrating both memory and logic functions, more extensive SoC solutions for mobile computing platforms have remained elusive because the PMIC and RFIC operate with two or more of high voltage, high power, and high frequency.
As such, conventional mobile computing platforms typically utilize incompatible transistor technologies that are specifically tailored for the different functions performed by the PMIC and RFIC. For example, laterally diffused silicon MOS (LDMOS) technology is typically employed in the PMIC to manage voltage conversion and power distribution (battery voltage regulation including step-up and/or step-down voltage conversion, etc.). Group III-V compound semiconductors, such a GaAs heterojunction bipolar transistors (HBTs), are typically utilized in the RFIC to generate sufficient power amplification at GHz carrier frequencies. Conventional silicon field effect transistors implementing CMOS technology then entail a third transistor technology utilized for logic and control functions within the mobile computing platform. In addition to fundamental semiconductor material incompatibilities between the various ICs in the mobile computing platform, transistor design for DC-to-DC conversion switches in the PMIC has been generally incompatible with the transistor design for high frequency power amplifiers in the RFIC. For example, the relatively low breakdown voltage of silicon requires source-to-drain separation in a DC-to-DC converter switch to be vastly larger than is permissible for a power amplifier transistor needing an Ft exceeding 20 GHz, and possibly up to 500 GHz, depending on the carrier frequency (e.g., WPAN is 60 GHz and so transistors need an Ft many times 60 GHz). Such different transistor-level design requirements render the fabrication processes for the various transistor designs distinct and difficult to integrate into a single process.
Therefore, while an SoC solution for the mobile computing space that would integrate PMIC and RFIC functions is attractive for improving scalability, lowering costs, and improving platform power efficiency, one barrier to an SoC solution is the lack of a scalable transistor technology having both sufficient speed (i.e., sufficiently high gain cutoff frequency, Ft), and sufficiently high breakdown voltage (BV).
Group III-nitride (III-N) devices offer a promising avenue for integration of PMIC and RFIC functions with CMOS as both high BV and Ft can be obtained. To date however, III-N transistors employ a 2D electron gas (2DEG), or sheet charge, as the transport channel. This 2D sheet charge is formed at the abrupt hetero-interface formed by epitaxial deposition of a film with larger spontaneous and piezoelectric polarization, such as MN, on GaN, for example. Because the polarization fields are highly directional, the 2D sheet charge only forms in the top (0001) wurtzite crystal plane at the hetero-interface. This material-based asymmetry poses a problem for implementing a multi-gate transistor architecture, such as the dual-gate and tri-gate designs now practiced in silicon by industry leaders. As such, the footprint of a III-N transistor may be disadvantageously large, and suffer various performance limitations akin to those that spurred the transition to non-planar silicon devices (e.g., short channel effects).